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MKlee2's avatar
MKlee2
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Quartus Prime Pro 19.4 error during Fitter->Place on Ubuntu 18.04 and 19.10 - "qspc_nldm_max_step_size=10.0 as a floating point value" - continues after second start

Whenever I try to compile a design I get the mentioned error right after Plan at the start of "Place"ing (Early Place = off). This happens on Ubuntu 18.04 and 19.10. The error in the attached log doe...
  • TJoha6's avatar
    TJoha6
    6 years ago

    I had this problem too with some versions of QuartusPro, at least 19.3, both on Linux Mint and CentOS, but could not find any answers in Jan-Feb.

    Today I found your posting and also this link: https://wikis.uni-paderborn.de/pc2doc/Noctua_FPGA_Usage,_Integration_and_Development

    which provide a possible explanation and fix.

    It is related to the linux LOCALE setting, if you use another format than US (in Europe, we use decimal comma, not point).

    By setting LC_NUMERIC= ="en_US.UTF-8", at least for the QuartusPro session, the problem disappears.

    /Ted

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi MKlee,

I have sent an email to you. Please let me know if you do not receive.

Thanks.

Best regards,

KhaiY

  • MKlee2's avatar
    MKlee2
    Icon for New Contributor rankNew Contributor
    6 years ago

    I finally got time for a few more tests:

    • My error example file from above compiles just fine now
    • My main design still crashes with the new error, when starting "Place" (but continues in a second run)

    So I started to remove ip after ip in my design and finally after removing all external memory ip's from my design the error was gone and it compiles in one go.

    So I guess the patch broke somthing in combination with this ip?

    I can also reproduce the said new error by using a (new) minimal design only containing some avalone-pipline bridges, a custom avalon-mm-master and the external memory ip.

    • IP: External Memory Interfaces Intel Stratix 10 FPGA IP
    • Connects a DDR4 RAM
    • Version 19.1.0
    • Simulation generation turned off (mentioning this cause the new error points to some stuff containing _sim in its name)

    If I find the time I will install the patch on window and compile the design there, to see if the error persists.