gchadwick
New Contributor
New ContributorQuartus Prime Lite 20.1 reports a compile error on valid systemverilog generate block syntax
The following system verilog produces an error in Quartus Prime Lite 20.1:
logic [7:0] foo;
for (genvar i = 0;i < 8; i++) begin : g_test
assign foo[i] = 1'b0;
end
The error seen is:
...
