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gchadwick's avatar
gchadwick
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5 years ago

Quartus Prime Lite 20.1 reports a compile error on valid systemverilog generate block syntax

The following system verilog produces an error in Quartus Prime Lite 20.1: logic [7:0] foo; for (genvar i = 0;i < 8; i++) begin : g_test assign foo[i] = 1'b0; end The error seen is: ...
sstrell's avatar
sstrell
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5 years ago

Just to verify, in the project settings, which version of Verilog have you selected for the compilation (under compiler settings)? Perhaps you have it set to an older compiler version that is causing the issue.

#iwork4intel

  • gchadwick's avatar
    gchadwick
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    5 years ago

    The language version is set to system verilog (under Assignments->Settings->Compiler Setting->Verilog HDL Input)