albertsun
New Contributor
4 years agoQuartus Prime Avalon SDRAM Controller - readdatavalid never asserting
I'm currently using the DE2-115 education board and implementing the SDRAM controller. When instantiating a read (from the Avalon MM documentation, I believe read requests are pipelined), the readdatavalid signal from the controller is never asserted even when read is asserted. I have tried both leaving the address and read asserted, and de-asserting the read signal after one clock cycle. I believe all the controller ports are connected properly, but I can't be 100% sure since I don't have access to a simulator. Thanks to everyone in advance.