Forum Discussion
AdzimZM_Altera
Regular Contributor
4 years agoHi Sir,
Do you see the waitrequest signal has been asserted after the read signal been asserted?
Do you see any difference when using burst operation?
I can assist you on Simulator (Modelsim) to simulate the design if you want.
But I need the design file and maybe some instructions.
Thanks,
Adzim