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albertsun's avatar
albertsun
Icon for New Contributor rankNew Contributor
4 years ago

Quartus Prime Avalon SDRAM Controller - readdatavalid never asserting

I'm currently using the DE2-115 education board and implementing the SDRAM controller. When instantiating a read (from the Avalon MM documentation, I believe read requests are pipelined), the readdat...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Sir,


Do you see the waitrequest signal has been asserted after the read signal been asserted?


Do you see any difference when using burst operation?


I can assist you on Simulator (Modelsim) to simulate the design if you want.

But I need the design file and maybe some instructions.

Thanks,

Adzim