Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi Jake,
My circuit does now appear to work as expected - before I was getting messages about logic contention, and I assumed because of the prior error message this was due to my lost buffers but ive taken a look at my VWF and there was a mistake with the simulated data from my 'memory'. Thanks for the link! Ill have good read of that before doing anything else on this.