Quartus optimizing away my buffers

You can ignore the message. I'm guessing you're simply misunderstanding the meaning of the message. I don't have your design so I can't dissect it for you but it appears you've declared the signals:

"Memory_Switch_Lite:inst8|TriState_Unidirectional_ Buffer_24Bit:inst26|lpm_bustri:lpm_bustri_componen t|dout"
"Memory_Switch_Lite:inst8|TriState_Unidirectional_ Buffer_24Bit:inst26|lpm_bustri:lpm_bustri_componen t|dout"

to be tri-state signals. Tri-state nodes do not exist in FPGAs (normally). They only exist at the IO pins. In other words, any tri-state signals used to drive internal FPGA logic will be converted to something (muxes, OR gates, wires, etc.) In your case, Quartus determined that these particular signals were always being driven from the specified locaiton and therefore simply turned them into wires.

If you want more details on the warning message, right-click on it in the report window and click "Help".

Jake