Quartus II Web Edition 10.0 SP1 : EDA Gatele level simulation

Hi,

I had read such informations in the forum and Altera's documentation, but this files have been created by the EDA Tools (or the simulator, i don't know) in the sub-repertory simulation/modelsim.

I put in attach file a zip, with the selector project, selector vhdl file and selector_test vhdl file. I had the sub-repertory simulation/modelsim.

The main strange thing is that the RTL simulation (trough the menu tools/run simulation eda tool/ eda rtl simulation ) is functional without warning.

The Settings/EDA Tool Settings for simulation are :

• Tool Name : ModelSim-Altera

• Format for output netlist : VHDL

• output directory : simulation/modelsim

• Map illegal HDL characters: on

• Compile test bench : T1 ==>

• top level module in test bench : selector_test

• Use test bench to perform VHDL timing simulation : on

• Design instance name in test bench : selector

• Run simulation until all vector stimuli are used : on

• test bench files : selector_test.vhd

I found an example for simulation with native-link and ModelSim-Altera in Verilog (Native_Modelsim_restored : multiplier project) and tried it with no problem for RTL and gate level simulation, so it seem's that it is not a problem with my version of Quartus.

So, i begin to have no more ideas.

thanks for your time,

EON