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Hello,
I'm new with the ModelSim-Altera (i' known well Max+Plus II and the embedded version of simulation in the previous version of Quartus).
I have readed Quartus Handbook and Help, lot of threads in the Forum but I did’nt found the answer. So I post this one.
I’ve reduced my problem to the smallest ones to simulate one selector (selector.vhd). After the proposed modification in the Assignments Settings menu (Format for output netlist è vhdl, Map illegal HDL character è on, Compile test bench è T1 for the use of the benches file : “selector_test.vhd”. The EDA Tool settings for simulation are turned on ModelSim-Altera, with VHDL format.
I’ve no problem with the RTL simulation, but some ones with the gate level ones.Modelsim (ModelSim Altera starter edition 6.5e) write in the transcript aera :
# Loading instances from selector_vhd.sdo
# ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
# ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./selector_run_msim_gate_vhdl.do PAUSED at line 12
What i forgot in the settings of Quartus II to use this new EDA-Tools (for me !)
Thanks and best regards
EON
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Hi,
Quartus generates two files for the modelsim simulation.
1. <toplevel_name>_vhd.sdo ( this file contains the timing information)
2. <toplevel_name>.vho ( this file contains your design gatelevel)
You need both file files for the simulation. I assume you forgot to include the
<toplevel_name>.vho file.
Kind regards
GPK
Honored Contributor
