Altera_Forum
Honored Contributor
18 years agoQuartus II v7.2 changes to Signaltap
Hello,
among other changes, with v7.2 the Signaltap embedded logic analyzer is said to be improved. Before I could evaluate any improvements, I was aware of some changes, that appear to me as unexpected step back. When importing a stp file from v7.1 that occupied 1195 LEs to v7.2, it was blown-up to 7621 LEs (it utilized segmentedx1 acquisition). Restricting the trigger to circular only, still 1477 LEs were needed. This means practically, that the segmented acquisition mode can't be used any more without a huge resource overhead. E. g., the said 1k LE stp example was used in an EP2C8 design, guess how many LEs are remaining here! Particularly the x1 segmented mode seems interesting to me as replacement for an otherwise missing clock qualifier with signaltap. (Fortunately THE competitor also has no clock qualifier with ILA core). At first look, it seems that v7.2 must not be used for some (resource critical) designs. Or did I overlook something important? Additionally, I'm missing a "save as v5 Signaltap file" option. For stp files, that don't utilize new options, the only difference is in the version number. Regards, Frank