Quartus II V12: .sdo files not generated or in nonexistent folder...don't know which.

hmm... well... i have quartus 14.1 with latest patch right now and have similar problems. while checking in compilation report -> EDA Netlist Writer -> generated files, only vo file is generated. not sdo. and in the same report directory but under messages pane it says: "Generated the EDA functional simulation files although EDA timing simulation is chosen" well... that explains why sdo is not generated.

altera's help site says:

"CAUSE: You attempted to perform a post-compilation timing simulation on the specified device; however, the feature is not supported in the Quartus II software. The Quartus II software generated the post-compilation functional simulation files instead.

ACTION: If you want to run post-compilation functional simulation, then set the eda_generate_functional_netlist assignment or turn on the Generate netlist for functional simulation only option in the Quartus II software."

keep your attention on a "specified device" part, altera guys simply did not created timing information for cyclone v.

Quartus II Handbook Volume 3: Verification 2014.12.15 says:

"Note:

Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level

timing simulation is not supported for Arria V, CycloneV, or StratixV devices. Use TimeQuest

static timing analysis rather than gate-level timing simulation."

so basically what they are saying is that "if you have timing issues then go ahead and mess with the timequest why are you simulating at all... -simulate only when you know that your timings are 100% healthy"

today's market is a cruel place men.... if there is something that a production can cut off from itself to spare expenditures, marketing managers will sniff it down and cut them.

advantage with timing simulation was that you could observe every logic cell, all the input signals, and their timings. and track down right to the output of the logic cell. this is something that timequest will never give you since it tells you delays between registers. not between logic cells. also it was helping to visualize the exact cause of an error. like on the simulation screen you could see all the signals and one of them was becoming red, indicating a timing violation; and observe the errors that followed because of that exact violated signal. eeh those were the days... but they are gone. :( i wanna kill myself. just as i wanted when quartus cancelled their internal simulator. farewell Modelsim's timing simulation... we had spent many sleepless nights together. you fought shoulder to shoulder with me so many battles. you will always stay in our hearts. ;( (<---it's a crying smile)