Forum Discussion
Altera_Forum
Honored Contributor
13 years agoYes, I have tried
Toolname: Modelsim-Altera Toolname: Modelsim (my true target) Format for output netlist: VHDL Output Directory: simulation/modelsim (the default) Output Directory: <my project>simulation/modelsim I've also ensured that under "More EDA..." I have turned "Generate netlist for functional simulation only" OFF. summary Output Directory: type_anything_you_like, OK/Apply results in Output Directory: simulation/modelsim (the default) and no directory is created