Quartus II Simulator

In the 'Node finder' the signal tmp_test only appears when filter is set to design entry. It doesn't appear in post-compilation. tmp_test is sourced from an unsigned and no output depends on it. This is the VHDL code :

ARCHITECTURE PCM3006_architecture OF PCM3006 IS

SIGNAL NEW_COUNT, COUNT : UNSIGNED (7 DOWNTO 0);

SIGNAL TMP_TEST : STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

NEW_COUNT <= (COUNT+1)MOD 256;

TMP_TEST <= STD_LOGIC_VECTOR(COUNT);

SYNC : PROCESS (CLK)

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

COUNT <= NEW_COUNT;

END IF;

END PROCESS;

END PCM3006_architecture;

tmp_test, count and new_count are removed after compilation.