Quartus II Simulator

Hello FvM, what do you mean by "tap each signal at its source" ? For example, in one VHDL entity I've got the following signal that I'd like to monitor on the quartus simulator :

signal tmp_test : unsigned (7 downto 0);

My design consists in one 'block diagram/schematic' file and a VHDL file (where is defined the tmp_test signal).

The only way I've found to monitor that 'tmp_test' signal is to output the signal to the schematic with a conversion using std_logic_vector and connecting that vector to output pins.

This is not too hard in a very simple project but in a more complex one this technique might be impossible.

Thanks.