In my experience with VHDL, Quartus will NOT search your libraries path for source files. All VHDL files MUST be in the file list (either directly, or a tcl file that picks up a file list from somewhere). I have no experience with Verilog on this issues, but I know that verilog has no libraries features built into the language, so it may search the directories in the libraries path for source files (verilog allows include files, like AHDL, whcih are probably pulled out of the library directories, because I know for AHDL you cannot include .inc files in the file list, they MUST be picked up from your libraries settings. Putting a .inc file in the file list causes a compile error because it is not a complete unit)
For VHDL, Quartus will only compile files in the file list. If you are using component instantiations, they are all treated as black boxes until the mapping stage. If the component cannot be mapped to an entity, it will not do any further compilations to try and find the entity or source file, it just throws an error. With direct instantiation, again, if the entity hasnt been compiled already, it will throw an error. Files in the libraries path are NOT compiled.
What exactly are you trying to do?