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Altera_Forum's avatar
Altera_Forum
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7 years ago

Quartus II Fitter error in connecting the output of IOPLL to refclk of ATX PLL

Hello, I am creating a Quartus project to transmit high-speed data using the Arria 10 Transceiver Native PHY. I am supplying the the serial clock (at 1.5GHz) to the tx_serial_clk0 using Arria ...
DGila's avatar
DGila
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

I am having a similar problem, the IOBUF/O output can't be connected to the CMU_FPLL_REFCLK_SELECT/REFCLK input

can I add BUFCLK/BUFCLKBLOCK to my design manually?

other suggestion is maybe to instanciate HSSI_REFCLK_DEVIDER, which I did not find.

Thanks,

Dror

druva1's avatar
druva1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi,

Where you able to fix this error? I am having the same issue :/..

  • Visshnu's avatar
    Visshnu
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    I am facing the same issue..

    Is there a way to fix this issue?

    • druva1's avatar
      druva1
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Are you using a template or an example? or your own design?

      Because in my case I used an Arria 10 Transceiver example and discover that is was a wire issue.

      In the example, two signals were exportered from the top level design and connected together in the testbech. So instead of exporting them, I contected them together in the top level.

      Cheers