Quartus II Compiler inferring latch for a DFF

Two async inputs for one logic element? It depends on the device family. For Cyclone II, no it is not. For some others, yes.

If you are using UDPs just to see what they are and can do, it could be a interesting thought experiment.

But as a practical logic implementation technique, IMHO you are going down a big rathole that is rather useless these days.

UDPs are so limited. Exactly one output port. One to ten input ports. No bus ports (ie, all ports are one bit wide). Either in or out, no bidir ports.

Instead of programming in a higher level language and letting the tool do the mapping, you are writing custom assembly language.

Personally I would say forget UDPs altogether and write in verilog at a higher level, but that is just my recommendation based on 40+ years of experience. YMMV.