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humandude's avatar
humandude
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3 years ago

Quartus II Compiler inferring latch for a DFF

I'm using a DFF module included with my Quartus II / ModelSim (web edition) installation in my Quartus project, but when I compile the project I get the following message: "Inferred latch for "q" ...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
3 years ago

You don't say what device family you are using. That is is pretty old version of Quartus, might it be Cyclone II?

If so, Cyclone II LE block only has one async control mode, either set or clear. Not possible to have both async clear and set inputs.

So Quartus can't map directly to that LE primitive DFF and has to synthesize it as a latch, if both clear and set are used.

That being said, why are you even using that DFF primitive in your source code? Why not just write the verilog for an inferred register?

wire clk, rst, d;
reg q;
always @(posedge clk or posedge rst) if (rst == 1) Q <= 0; else Q <= D;
  • humandude's avatar
    humandude
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    3 years ago

    Are you saying it is not possible to have two async control inputs for one logic element? I would imagine the compiler would create the necessary mapping to generate as many control inputs the user decides to implement, possibly using more than one LE if necessary. I'm not sure, but that's my thought process.

    I was able to get past the inferred latch issue by making one change to the UDP (dffep.v). That is, I replaced every instance of "?" with "x". Seeing as that stopped the inferred latch warning, I can only assume that the compiler does not know how to deal with a value that can be 0, 1, or x. But it can interpret a value that can be either 0 or 1. Writing code for a DFF is easy, but I think there's much to learn about user defined primitives and how Quartus deals with them!