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Does anyone have experience with making new components for SOPC Builder in Quartus II 7.1?
I've had good luck with generating components for SOPC Builder when they are simple modules that span a single file.
However, I've noticed that that component wizard does not allow for designs that span multiple files. Now if I copy each module into a single file, everything works fine. But that's not conducive to design reuse. Has anyone found a solution to this?
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I have a similar problem where I'd like to create a single file VHDL component that uses a package for defining some common types/constants used in this file. This used to work fine in pre 7.1 SOPC for the analysis of files in the component editor wizard because you could add multiple files. However, i can only specify a single file for this now and hence when it analyses the component file that uses my package it fails with errors.
I have also come across the problem with multiple files and the change in bahaviour. I have to explicitly add each file in Quartus or add a project library path in order to compile.
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Also, I've noticed that sometimes the component wizard has trouble determining the size of the address bus when using generics. Has anyone heard of this problem?
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I also have a problem with components that define variable data and address widths with generics using the new 7.1 component method - *_hw.tcl. This worked fine using the legacy .ptf method pre 7.1. For example, a generic defining the address width for a simple test component with a master port and adding this component with an address width setting of 32 to try and access internal memory I get the error :
Error: PP_AvalonDummyMaster_3.dummy_m: "onchip_mem_1.s1" (0x10010000..0x1001003f) outside range (0x0..0x1)
The onchip memory for this test is 64 bytes located at 0x10010000.
Can anybody help?
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