Quartus II 13 synth. a SV comp. which uses an interface and attach to testbench, How?

Hi,

I've looked around on this forum and google, but have come up empty. (There may be a keyword I'm missing but I am here now:)

I have a component of a larger design that I want to synthesize and test. but it is defined like this:

interface my_component_if;
  logic my_sig;
  logic my_other_sig;
  // etc...
  modport comp (input my_sig, output my_other_sig);
endinterface
module my_component (my_component_if.comp mcif);
// insert liberal use of interface
endmodule

When I synthesize the component the ports get flattened out to the following:

module my_component (
  \my_component_if.my_sig ,
  \my_component_if.my_other_sig
);

My testbench has the following:

// make instance of int, and comp, then string em together.
my_component_if mcif();
my_component DUT(mcif);

Modelsim comes back with the following (not the same module as listed above):

--- Quote Start ---

# ** Warning: (vsim-3017) testbench/my_comp_tb.sv(35): [TFMPC] - Too few port connections. Expected 9, found 1.

# Region: /my_comp_tb/DUT

# ** Error: (vsim-3906) testbench/my_comp_tb.sv(35): Connection type 'interface my_comp_if# ()' is incompatible with 'wire[31:0]' for port (\mcif.rdat2 ): Can't mix packed and unpacked types.

# Region: /my_comp_tb/DUT

# Error loading design

--- Quote End ---

Modelsim is from MG.

Again, this is just a piece to a larger design, and there are a lot more to test. I want to test along the way but this is just no fun having to make a TB for simulation then making another to test synthesized version.

What is the best way to not have this suck so bad? Is there a setting in Quartus that will let me keep the interface to connect to the TB? Or

a setting that will map a synthesized module to a TB that uses an interface. Maybe a modelsim setting? surely this isn't a new issue?

Thanks.

-EV