Forum Discussion
6 Replies
- Altera_Forum
Honored Contributor
Web editions never had virtual pins (what I remember) but I installed the 10.1 Web version using the Altera Installer (at the download subscription page) and found the virtual pins feature enabled.
- Altera_Forum
Honored Contributor
Well, it's kind of strange. I have a design which has lots of virtual pins, which compiles fine on 9.1sp2; but when I load it in 10.1, even though it *recognises* the virtual pin assignments in the editor, I get a warning during compilation that virtual IO will only be enabled in the subscription version, and when I compile I end up with an error saying that it is missing 133 output pins to accomodate for all the pins I'm trying to use (which were supposed to be virtual pins of course, but didn't register as such, apparently).
- Altera_Forum
Honored Contributor
as far as i understand, Virtual Pins are supposed to be unique to Subscription Edition since they are part of the Incremental Compilation flow
- Altera_Forum
Honored Contributor
Then they slipped up on the restrictions of Quartus II 9.1sp2 Webedition, because it definitely worked there.
- Altera_Forum
Honored Contributor
you may file an enhancement request in an SR. Virtual Pins (or something similar) are useful for doing resource or timing estimates even though they are intended for use in Incremental Compilation
- Altera_Forum
Honored Contributor
Maybe Altera now and then surprises someone to get them hooked :lol:
Seriously, Monday night I installed the WebEdition 10.1 using the Altera Installer program on the download page of the Subscription Edition. Once that started I changed the wanted installation into Web Editiopn, and let the thing do its job (and watched Top Gear or something). Yesterday I did a pin-study on a project with DDR2 and PCIe IP and to my surprise it didn't choke on the virtual pins, here is the Flow Summary:
I must mention that I have an expired Subscription License File for QII9.1 active, but the Installer did that all on its own. From the other side it will only use one CPU core, but time we can make free, virtual pins is a different story. I hope Altera isn't watching, and taking my virtual pins back :)Flow Status Successful - Tue Dec 07 18:29:52 2010 Quartus II Version 10.1 Build 153 11/29/2010 SJ Web Edition Total combinational functions 2,951 / 21,280 ( 14 % ) Dedicated logic registers 1,928 / 21,280 ( 9 % ) Revision Name rr4gx15 Top-level Entity Name rr4gx15 Family Cyclone IV GX Device EP4CGX22BF14I7 Timing Models Preliminary Total logic elements 3,296 / 21,280 ( 15 % ) Total registers 0 Total pins 61 / 81 ( 75 % ) Total virtual pins 671 Total memory bits 8,512 / 774,144 ( 1 % ) Embedded Multiplier 9-bit elements 0 / 80 ( 0 % ) Total GXB Receiver Channel PCS 1 / 2 ( 50 % ) Total GXB Receiver Channel PMA 1 / 2 ( 50 % ) Total GXB Transmitter Channel PCS 1 / 2 ( 50 % ) Total GXB Transmitter Channel PMA 1 / 2 ( 50 % ) Total PLLs 2 / 3 ( 67 % )