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Altera_Forum
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12 years ago

Quartus II : Problems with VHDL records?

I have a problem with the synthesis of my design: A component has an AXI slave interface. In the architecture of this component the AXI signals are being combined into a record an then assigned...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Unfortunately I cannot show the code. But I could solve the problem. Apparently it was the AXI record. After I removed the record and assigned all signals individually Quartus did not report any more errors