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Altera_Forum
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12 years ago

Quartus II : Problems with VHDL records?

I have a problem with the synthesis of my design: A component has an AXI slave interface. In the architecture of this component the AXI signals are being combined into a record an then assigned...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Are you sure about the multiple drivers? I think its a multiple driver problem if you drive different record elements from different processes, or different bits of a record element.

Does the design simulate ok? do you get any 'XXX' values anywhere?

Can you show the code with the declaration of the record and where it is used/assigned?