Forum Discussion
Quartus Gate Level Simulation mismatch with RTL Simulation
Altera Board: DE0 Nano SOC
Xilinx Board: Nexys 4 DDR
I have implemented some RISC-V cores in VHDL and SystemVerilog based on Gaisler VHDL and uploaded to Github repositories:
https://github.com...
RichardT_altera
Super Contributor
Super ContributorHi ,
Sorry for the delay in response. Do you still need help on this?
Have you check whether the timing is clean in your design?
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
