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Anonymous's avatar
Anonymous
4 years ago

Quartus Gate Level Simulation mismatch with RTL Simulation

Altera Board: DE0 Nano SOC Xilinx Board: Nexys 4 DDR I have implemented some RISC-V cores in VHDL and SystemVerilog based on Gaisler VHDL and uploaded to Github repositories: https://github.com...
RichardT_altera's avatar
RichardT_altera
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4 years ago

Hi ,

Sorry for the delay in response. Do you still need help on this?

Have you check whether the timing is clean in your design?

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.