Quartus cannot properly interpret VHDL2008 select? statements.
Hello,
I'm attempting to make my own RISC V processor, and part of that is selecting the correct OPCode, I have the following VHDL which is supposed to do this:
--/-----------------------------\ --| OPCODE INSTRUCTION DECODING | --\-----------------------------/ with fetched_instruction select? next_decoded_opcode <= LB when "-----------------000-----00000--", LH when "-----------------001-----00000--", LW when "-----------------010-----00000--", LBU when "-----------------100-----00000--", LHU when "-----------------101-----00000--", SB when "-----------------000-----01000--", SH when "-----------------001-----01000--", SW when "-----------------010-----01000--", BEQ when "-----------------000-----11000--", BNE when "-----------------001-----11000--", BLT when "-----------------100-----11000--", BGE when "-----------------101-----11000--", BLTU when "-----------------110-----11000--", BGEU when "-----------------111-----11000--", JALR when "-------------------------11001--", JAL when "-------------------------11011--", Addi when "-----------------000-----00100--", SLLI when "-----------------001-----00100--", SLTI when "-----------------010-----00100--", SLTIU when "-----------------011-----00100--", XORI when "-----------------100-----00100--", ORI when "-----------------110-----00100--", ANDI when "-----------------111-----00100--", SRLI when "-0---------------101-----00100--", SRAI when "-1---------------101-----00100--", ADD when "-0---------------000-----01100--", SUB when "-1---------------000-----01100--", inst_SLL when "-----------------001-----01100--", SLT when "-----------------010-----01100--", SLTU when "-----------------011-----01100--", inst_XOR when "-----------------100-----01100--", inst_SRL when "-0---------------101-----01100--", inst_SRA when "-1---------------101-----01100--", inst_OR when "-----------------110-----01100--", inst_AND when "-----------------111-----01100--", AUIPC when "-------------------------00101--", LUI when "-------------------------01101--", CSRRS when "-----------------010-----11100--", -- NEEDS IMPLEMENTATION-- CSRRW when "-----------------001-----11100--", -- NEEDS IMPLEMENTATION-- CSRRC when "-----------------011-----11100--", -- NEEDS IMPLEMENTATION-- CSRRSI when "-----------------110-----11100--", -- NEEDS IMPLEMENTATION-- CSRRWI when "-----------------101-----11100--", -- NEEDS IMPLEMENTATION-- CSRRCI when "-----------------111-----11100--", -- NEEDS IMPLEMENTATION-- INVALID when others;
However, even though inside Quartus, the file is marked as a VHDL2008 file, synthesis still fails, citing that:
"Error (10500): VHDL syntax error at controller.vhd(159) near text "?"; expecting "(", or an identifier, or a string literal"
The above statement synthesizes completely fine within Xilinx's Vivado, so I'm not quite sure what Quartus is trying to see that Vivado can handle.
Why is Quartus having issues with the 'select?' clause, and what can I do to remedy this while maintaining the syntax (eg: I still want to use with/select? and have the wildcards available for easy reading)