Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHad a similar problem today with the DDR SDRAM High Performance Controller.
In my case the sdram settings in the .qsf file were (intentionally) incomplete (because of some problems I met in the past). I re-ran the sdram_pin_assignments.tcl script and adapted the pin names to match those of my design + (specific to my design) changed the OUTPUT_TERMINATION to "SERIES 50 OHM without CALIBRATION". I also noticed a (perhaps 2) new entry(/ies) in the .qsf file : set_instance_assignment -name T11_DELAY 7 -to <pin_name> and set_global_assignment -name MISC_FILE <filename>.dpf (which contains indications about the clock pins of the sdram). Since then the fitter passes. Regards, P9