Quartus 9.0sp2 compiler bug

I could verify, that Quartus produces different code with a larger device, e.g. a MAX7160S. I also could see, that SimCount registers aren't inferred in the 103 macrocell version. My first thought was, that the issue is related to the usage of unitialized variables instead of regular signals for two counters in the simulatorca process. But the behaviour with signals is identical. Thus it seems to be a bug.

I know, that a CPLD logic synthesis is considerably different from FPGA synthesis in Quartus (Max II is actually a small SRAM based FPGA with non-volatile configuration memory rather than a CPLD).

I could trace back the issue back to Quartus V6.0, that showed similar behaviour, while in V5.1, the simulation output was different. The macrocell consumption was still different between 7128and 7160, so I fear, that part of the design has been also removed in this version.