Quartus 20.1.0 Synthesis of System Verilog Interfaces

Hi Richard -

I'm unable to give kudos again for some reason - i get the white circle with a bar.

That is a great reference for interfaces within quartus - but it confirms the two things I am indicating - quartus doesn't handle logic within the interface, and the documentation stopped indicating levels of support for system verilog in version 17.0.

If you look at the templates, the ones that contain logic are actually *outside* of the interface. I personally cannot see a reason for this from a synthesis point of view. Quartus models (from the netlist viewer) Interface logic as a separate block, that acts like a 'punchboard' of wire connections. Each interface port when instantiated to a cone of logic, become a buffer within an RTL build.

I have to accept whatever is decided in Santa Clara. Given that, when logic is inserted, and accepted by most other tools, when Quartus reads that RTL, it doesn't produce an error or warning, indicating that RTL logic in interfaces is an issue. The only sign I saw was that Quartus would put warnings on wire assignments in interfaces connected to interface logic that the wire assignment had no initialization, from a synthesis and even a copper perspective, doesn't make sense at all.

So if Quartus doesn't support synthesis of logic in templates (which the interfaces you provided seem to confirm) it should error when any interface contains logic.

Yes, I submit feedback regularly. Thank you for your response.