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Occasional Contributor

4 years ago

Quartus 20.1.0 Synthesis of System Verilog Interfaces

I have basic interfaces with modports as below: interface if_memory ( ); logic valid; logic strobe; logic wren; logic [31:0] address; ...

Super Contributor

4 years ago

This case will be closed because it was duplicate with an existing case. Please refer to the case below (link attached) for further support.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.