Forum Discussion
bitstreamer
Occasional Contributor
Occasional ContributorQuartus 20.1.0 Synthesis of System Verilog Interfaces
I have basic interfaces with modports as below:
interface if_memory ( ); logic valid; logic strobe; logic wren; logic [31:0] address; ...
RichardT_altera
Super Contributor
Super ContributorThis case will be closed because it was duplicate with an existing case. Please refer to the case below (link attached) for further support.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
