Quartus 18.1 still broken.

Hi,

we appreciate your efforts and patience.

we request you all, for better support,please open multiple threads instead of single thread with multiple queries.

Step 1 : With reference to Fig. 6 :

please first modify the .lst file(Since it is temporarily solution) as suggested in Fig .9 from the installed directory & path may similar like below & check screen shots as well,

C:\intelFPGA\18.1\ip\altera\ethernet\altera_eth_tse

Step 2 : from "Upgrade Tool" click on "Failed" IP & generate again..

Step 4 :

"When I attempted to attach the .lst files, the ANSWER button was grayed out, so I added a .txt suffix (yet another issue with the forums)."

I also realized same behavior & it might happen during maintenance or .lst is not supported.

Step 5:

"When I do a File -> Open on MAIN_PLL.vhd (the generated core) it just opens MAIN_PLL.vhd (same for EMAC.vhd) instead of the wizard. Things like the FIFO open in the wizard as expected."

Now check below,

Step 6:

Successfully upgraded & Compiled.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)