Honored ContributorHi!
Since the introduction of the new RTL viewer with Quartus 13.1, the bits are shown in reverse order, i.e. instead of 16'h0001 it shows 16'h8000. Is it happening to anybody else? Any way to fix it? Thanks!
Honored ContributorHello
Yeah I can see this too in the Technology Map Viewer i.e post fit netlist viewer. I can also confirm I see this in hardware using SignalTap! :mad: I have never had a problem with this up to Q2 12.1 so at the moment I am not sure what is going on, I may revert back to this version of Quartus if I can't sort this imminently.Honored ContributorAt least in signal tap you can make a "right mouse click" on the signal's name and choose between "MSB on Top, LSB on Bottom" or "LSB on Top, MSB on Bottom" to reverse the bit order to get the correct representation displayed... I had same issues as I tend to define the vector as x downto y (e.g. 15 downto 0 with Bit15 being MSB) rather x to y (e.g. 0 to 15 with Bit 0 being MSB)...
Honored ContributorThat is an interesting point, I have never noticed that before in SignalTap and explains a lot with the debugging I was doing yesterday. Is this different to previous QuartusII versions because I have been using SignalTap since Quartus2 v8 and I have never had to change the MSB/LSB representation for std_logic_vector's?
Honored ContributorDoes altera read these forums? Is there any way to send this "bug report" to them directly?
Honored ContributorAltera is aware of this problem and working on a solution, which will be release in one of our V13.1 updates.
We do read this forum, but the official way to report a bug is to file a Service Request at http://www.altera.com/supportHonored Contributor
