Forum Discussion

New Contributor

6 years ago

Quartus中的路径约束

Hi，我需要在Qartus 18.1中做3个信号的路径约束。将三个寄存器的输出连到3个相邻的管脚上，要求3个信号的延时相同，最好走的路径也相近，请问怎么约束？

Regular Contributor

6 years ago

Hi,

You may use the set_max_skew constraint to perform maximum allowable skew analysis between sets of registers or ports.

If you want to set the maximum allowable delay, you may use set_max_delay to specifies a maximum delay exception for a given path.

Thanks.

Best regards,

KhaiY