Qsys

Thanks BadOmen,

I appreciate your thoughts and recommendations - and most certainly know the value of standard interfaces IP reuse and scalability.

However the FIFO at the input to the ALTGX will further scramble the timing of the GX output when a "set" is changed. In my application (which is not a communication of data)

It is critical that that upon a switch of bit sets the current bit position of the serializer is maintained - it simply sends the bit value form the new sequence.

In theory, the correct implementation of the function that I need is with a MUX 128:1 and a free running 7 bit counter that cyclically addresses the MUX at the output clock rate. In this way a change in the data at the input of the MUX changes the output stream immediately - as in the next bit state.

Unfortunately I have to use the ALTGX mega-function to access the high speed data rate hardware and high speed PLL - it was designed with a data communication in mind. It already forces me to live with its internal 4 word deep FIFO logic and the associated latency (the time it takes for the ALTGX FIFO to fill up with the new data when bit sets are switched) this results in an unavoidable skew.