Qsys

Thanks for your quick replay BadOmen,

Yes you are correct - I need to design a pure (no added bits) cyclic serializer which outputs a hardware selected set, from a pool of 32 pre-programmed sets, of 8 16bit words=128bits on a serial line at 2.5Gbps.

The hardware selection is time critical - the switch between sets must occur in one data clock cycle without resetting the FIFO or word counter. In fact that is all what I use the Cyclone IV GX for at this stage of the project.

The first part of your answer is related to the data path - that part is actually not what I had the difficulty with. I defined an on-chip 1port ROM MegaWizard instance which has separate data and address interfaces. I connected its data output using Avalon ST master signal type to the ALTGX transmitter data input which is an Avalon ST slave.

I have difficulty with the addressing of the ROM - in Qsys - I do not know how to form the address bus from two sets of lines coming from independent sources (3 LSB lines from the cyclic word counter and 5 MSB lines from FPGA input pins driven by an external controller in hardware)

I'n looking at the SGDMA component you suggested as a different approach for the cyclic data transfer - from first impression it looks much more complex then my (Naive?) system concept.