Qsys

If I understood what you are trying to do I think you would be best off with a comonent that has an Avalon-MM master on one side and an Avalon-ST source on the other side so that you could do something like this:

RAM (slave) --> (master) <your custom component> (source) --> (sink) FIFO --> whatever this goes to

Doing so will allow you to re-use a bunch of pre-existing components and you also will not have to worry about building your own interconnect. By wiring everything using conduits you kinda defeat the purpose of using Qsys since you could do that in HDL yourself. In Qsys you use standard interfaces and let the tool build the rest for you.

Also by the sounds of that repeating pattern of reading back 8 words then cycling back to the start sounds a lot like the 'parked reads' feature of my modular SGDMA. You can find it in the alterawiki, there is also an example of using the parked reads feature in the video frame buffering design I posted in the wiki since that's how I perform frame buffer repeating in that design.