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Interesting but it will be followed by a tidy work aligning data/address of your custom component with your bus. It might be feasible for Memory Mapped connection but it is certainly tricky for Avalon-ST connections. Giving that timing adapters are "freely" provided by Qsys.
Qsys is a good tool in general (one should not focus with only one aspect that failed), not yet mature and I am sure it will be better in newer versions of Altera design tools.
I managed to incorporate a custom JPEG encoder in a Qsys subsystem. I created the (_hw.tcl) file with SOPC builder. Then I added the folder that has the RTL and TCL files under the subsystem path. Qsys recognized the tcl file and displays the component in the top left among other components. I tested it and it worked.
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I've worked on a couple of SOPC systems and although I thought it was really powerful, the setbacks due to GUI issues really leaves me feeling like looking for alternatives. The last system used their Ethernet MAC. Our stuff resides outside QSYS and inside is the MAC with the necessary ST modules and signals, which eventually get exported to our modules. You're doing well by working in only the TCL and HDL files. Its is a good idea as long as you have the knowledge and keep it fresh in your mind. I have to leave this design in another companies hands and staying away from the internal workings of Qsys has been working well.
Cheers
Honored Contributor
