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Altera_Forum
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11 years ago

QSYS flattens our design hierarchy

Hi all, We are migrating from Xilinx to Altera and so far everything is running ok. As an alternative to Xilinx IP-integrator, we've now moved to QSYS. Here we get problems. First issue: I...
Altera_Forum's avatar
Altera_Forum
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11 years ago

@krasner: we have build up an extensive library over the years. Renaming files will take a lot of time and effort. Furthermore, company policy says that if we change sources, we will have to re-verify, re-validate and re-test all this legacy code: more effort.

VHDL libraries have been there like forever and use of them is perfectly valid VHDL: why doesn't Altera support this properly?? We want to migrate from Xilinx (Vivado) IP-integrator -that has no issues with libraries at all-. I am having a hard time selling this to my superiors...

@Dave: I have tried that. The problem is that Qsys only copies the .qip file, not the VHDL sources. As a result the .qip file does not work, because it contains relative paths like below: 

set_global_assignment -name VHDL_FILE -hdl_version VHDL_2008 -library UdpToFrame

A big difference I've noticed when migrating from Xilinx to Altera is that in Wuartus II you can configure and tweak EVERYthing... So why is Qsys offering so little settings???