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Altera_Forum
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10 years ago

QSYS flattens our design hierarchy

Hi all, We are migrating from Xilinx to Altera and so far everything is running ok. As an alternative to Xilinx IP-integrator, we've now moved to QSYS. Here we get problems. First issue: I...
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Altera_Forum
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10 years ago

I've noticed similar annoying "features" with Qsys and VHDL. Using a .qip file to describe your IP can solve both of your problems. The .qip file can be dynamically generated from Tcl if you have machine-specific installation differences.

Here's how the .qip solved my particular problems:

1. Qsys copies HDL files

If you use a .qip file, Qsys copies (or generates) a .qip file in the qsys_system/synthesis directory, and that file can reference the source code (in source version controlled folders).

2. VHDL libraries

You can specify the VHDL library to compile source into in a .qip file.

I *think* these are shown in the example file I posted in this thread ...

http://www.alteraforum.com/forum/showthread.php?t=48802

If not, ask and I'll try to post something a little more complete.

At least you know what you want to do is possible now :)

Cheers,

Dave