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Altera_Forum
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10 years ago

QSYS flattens our design hierarchy

Hi all, We are migrating from Xilinx to Altera and so far everything is running ok. As an alternative to Xilinx IP-integrator, we've now moved to QSYS. Here we get problems. First issue: I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I don't fully understand your library concern. Say you start a qsys file: IP.qsys, then when you generate all your files will be generated into IP/synthesis/submodules and the .qip file will specify set_global_assignment -library "IP"

Are you trying to generate several IPs at once and want to distribute them into different folders? Why can't you generate 1 IP at a time, and each time start a different qsys file?