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Altera_Forum
Honored Contributor
Honored ContributorQSYS flattens our design hierarchy
Hi all, We are migrating from Xilinx to Altera and so far everything is running ok. As an alternative to Xilinx IP-integrator, we've now moved to QSYS. Here we get problems. First issue: I...
Altera_ForumHonored Contributor
Honored ContributorI think it is possible to have Qsys generate into folders. I say this because if you instantiate code generated from Altera's DSP builder, it will be allocated into folders in the /synthesis/sudmodules/ path.
However, if you are using component editor (the GUI), there might not be a way to set this property. You will have to manually edit the "component"_hw.tcl file that qsys uses to set this information in. When looking through this tcl file I see a command: add_fileset_file "vhd design file path" VHDL PATH "another vhd path" Normally I see add_fileset_file command on their own so these get flattened in the submodule folder. I think the VHDL PATH command is the key because it specifies the path within the submodule folder where the vhdl file will be placed. But you will have to edit the _hw.tcl file by hand. Hope that made sense...
