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Altera_Forum's avatar
Altera_Forum
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11 years ago

QSYS feature-request: timing interface type

Hi all, given the version 15's interface-types, it is unnecessarily difficult to distribute control signals in a (nested) QSYS component and thus implement serial data processing. Streaming dat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

As a Tcl user you will love MyHDL - as it is Python ;)

If you need a hand, you can find me on all MyHDL channels (GitHub, IRC, Gmane)

Regards,

Josy