Honored Contributor
Honored ContributorOK, I've made a rough diagram of the design I'm working on, to illustrate the problem.
Light-Blue boxes are QSYS-components. Grey-boxes are QSYS-subsystems. Blue arrows is the data-plane, dark-blue is parallel data transfer (one transaction per cycle) and light blue is serial data transfer (23-bit values in 23 cycles, lsb first). All of these are avalon_streaming. You see that the data-plane is made up of point-to-point connections. Sometimes a component has incoming connections from two different source components (a directed graph). The pink connections are the clock/reset-"tree". Clock and reset distributed in a hierarchical manner and do not follow the data signal. As data-signals are useless without associated clock, QSYS has provisions to keep track of the clock-associations of these signals and will complain, if you try to connect signals with different associations. All components in "loop-controller" work on serial data. The synchonization on a common 506-cycle schedule is provided by a "synchronizer" (orange color) components, that delivers not only a schedule-counter, but also helper-signals (read/write-enables, adresses for different adessing-schemes and so on), a total of 28 bit control-bus. Feeding these control signals through avalon_streaming is not a good idea. Not all receivers need all signals. Components with two inputs (like the "costas" component) would also need to decide on which version of the control signals to act, it receives from "preserve" and "quotient". It is of course possible to ignore one set of control-signals, but as a component-designer, I would like to enforce that both inputs are synchronous with respect to the same control-signals. It would be much more adequate to distribute these control signals in a tree. Now the problems with the tree:
