New Contributor
Super ContributorPeng,
Seem Qsys cannot handle undefined required signal for AXI4. You should declare the list signal in order to error free. What are trying to do with module with only read signal? Handshaking happen seem not proper if that so.
New ContributorThanks,
My module will only do axi master read from the downstream. It doesn't perform axi write data to the slave, so there is no point to have axi master write signals in the top HDL. It is a very common design, for example memory map to stream (MM2S) DMA.
My model doesn't have only 'read' signals. As you can see in my attached picture, the module has all read channel signals.
BTW, this module works in Xilinx Vivado. It is just not supported in Quartus.
