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Honored Contributor
Honored ContributorQsys error : has write interface but no write control
Hi , I am trying to create a new component on Qsys , using my verilog code. The problem is that after I select the interfaces and the kind of signals , an error :"Has written interfaces but not write...
Altera_ForumHonored Contributor
Honored Contributora memory mapped interface would be used when you are trying to write data using an avalon bus to a memory location in your component. An example of the type of inputs and outputs for an memory mapped interface would need : clk, reset, address, write, writedata, read, readdata, waitrequest, readdatavalid etc.
This doesnt look like what you are trying to do. Quote from the pdf i linked: "Avalon Conduit interfaces group an arbitrary collection of signals. You can specify any role for conduit signals. However, when you connect conduits, the roles and widths must match and the directions must be opposite. An Avalon Conduit interface can include input, output, and bidirectional signals. A module can have multiple Avalon Conduit interfaces to provide a logical signal grouping. Conduit interfaces can declare an associated clock. When connected conduit interfaces are in different clock domains, Qsys generates an error message" If you just want your signals passed in and out of your component in your own way then perhaps a conduit would be appropriate.
