Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Qsys-DDR2_SDRAM Configuration

Hi, I´m new in the IP Core design. I`m using a Cyclone III 3C120 Development Board and now I want to design an IP Core with the following parts: clock source, Nios II Processor, Character LCD, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks, I tried it and it works.

But I need to fit also the "Read to Precharge time(tRTP)" from 7.5ns to 8.8 ns.