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Altera_Forum
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14 years ago

Qsys-DDR2_SDRAM Configuration

Hi, I´m new in the IP Core design. I`m using a Cyclone III 3C120 Development Board and now I want to design an IP Core with the following parts: clock source, Nios II Processor, Character LCD, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Lower the frequency of memory controller in DDR2 component settings. I've tested the same board with 125MHz and it worked fine.