Qsys Avalon bus symbol width

Hi,

I have a question regarding the Avalon bus symbol width.

First, I have a custom IP with Avalon bus data width 576 bits. And I connected Avalon BFM to it in order to simulate it and here is where the problems begin.

First of all, the BFM does not allow any other "number of symbols" than the power of two: 32, 64, 128. Ok, this is fine. To achieve the 576 bits data width I changed the symbol width to 9 in BFM and also in my custom IP. So my custom IP has 576-bit data buses and 9-bit symbols: 576/9=64 symbols. And the same for the Avalon memory-mapped slave BFM: 64 9-bit symbols. Both, the slave BFM and my custom IP are using "WORDS" as the addressing unit. But Qsys keeps complaining that I can not connect buses with different symbol widths regardless I have the same symbol width set up for both. And it also complains that the master address range is insufficient.

So I made another simple system with two BFM-s, master and slave. And just connect those. If I use the symbol width 8 in both BFM-s everything is fine. But without changing anything other than the symbol width in both of the BFM-s to 9 the Qsys issues an error that the slave's address range is outside of the masters. Again, both BFM-s use exactly the same settings and everything is OK with the symbol width 8 for both.

So, question? Is there something that I overlook or maybe there is a bug in the Qsys while using some "custom" symbol width?

The Qsys version I'm using is 21.1 build 169, shipped with Quartus pro. And the project is targeting Arria 10 family.

BR, Madis