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Altera_Forum
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13 years ago

Qsys address map granularity

What is the unit granularity is for the address range shown in Qsys address map? I have instantiated a generic_tristate_controller and tristate_conduit_bridge to interface an external Cypress ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Qsys generates address maps based on the width of the address signal/port at each component on avalon. The addressing scheme is to route RD/WR transactions around the bus to the right peripheral, which is nothing more than muxing to the correct set of physical address lines.

The 18 address lines to the SRAM can access 2^18 or 262144 locations, each location being 16bits wide; hence the 512kByte memory space.