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dadduni's avatar
dadduni
Icon for New Contributor rankNew Contributor
4 years ago

Qsys 20.1 does not see RECORD type as port

Hi everyone,

I have my top entity design using input and output ports with record type put in a package.

The synthesis and simiulations are totally fine but, when i try to import my design in the Platform Designer to connect it with a Nios2, the "new component" wizard does not display the port put in the records.

All the other ports are fine and the file also update correctly if modified, all the ports that are put in a record are ignored and I can't proceed.

Is this a known issue? Is there a workaround? Im using Quartus 20.1 Lite Free edition.

Waiting for your answer,

Davide

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Can you post your code and what you're seeing? It's not clear from your description what's going on.

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Can you provide the following so I can better understand your problem:

    1. Snapshots of your error
    2. (Assuming you're using VHDL) Which version of record data port are you using?
    3. What steps did you take to import your design to Platform Designer?


    Thanks!


    • dadduni's avatar
      dadduni
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi,

      I'm attaching the screenshots. The first one shows how the synthetizer understands correctly the group of signals as input port even if the signals are in a record.

      The second photo shows the Platform Designer Wizard in wich I imported the exactly same files, but he doen't see any input port because of the record. If i put the signals inside the top entity without putting them in a record the platform designer works fine.

      the top entity with record as ports:

      entity IM_AXI4L_S is
    generic (
        G_NREG : positive := 16
    );
    port (
        SAXI4LINT_i_ACLK    : in  std_logic;
        SAXI4LINT_i_ARESETN : in  std_logic;
        SAXI4LINT_i_AXI4LM  : in  TR_AXI4L_M;
        SAXI4LINT_o_AXI4LS  : out TR_AXI4L_S;
        SAXI4LINT_o_CONTROL : out TA_AXIREG(G_NREG-1 downto 0)
    );
end IM_AXI4L_S;

      the record definition:

      type TR_AXI4L_M is record -- AXI4-Lite signals driven by master interface
        ARADDR  : std_logic_vector(ciAxiLiteAddrWidth-1 downto 0);
        AWADDR  : std_logic_vector(ciAxiLiteAddrWidth-1 downto 0);
        WDATA   : std_logic_vector(ciAxiLiteDataWidth-1 downto 0);
        WSTRB   : std_logic_vector(ciAxiLiteStrbWidth-1 downto 0);
        ARVALID : std_logic;
        AWVALID : std_logic;
        WVALID  : std_logic;
        RREADY  : std_logic;
        BREADY  : std_logic;
    end record;
    • Nurina's avatar
      Nurina
      Icon for Regular Contributor rankRegular Contributor
      4 years ago

      Hi,

      We did not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

      Regards,
      Nurina

      PS: If there's any helpful answer given by the community or Intel Support, feel free to give Kudos.