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Hi there,
I have a design that sometimes has twice the compilation time as it usually does (even with just minor changes). It happens when the first or even the second routing attemp fails. Is there a report to show why the routing fails so that maybe I can polish my design so it is easier to route? Or is that any general design guidelines that will make the design more routing-friendly?
The interconnect usage of the design is only 26% of the avaliable device resources.
Thanks,
Hua
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Hi Hua,
the best way to find the routing problem is to use the tool "CHIP PLANNER".
In order to see the routing congestion you have to change the tool seeting.
Start the "CHIP PLANNER"
Under "View" select "Layer Settings"
Select "Routing Utilization"
Change the threshold value in order to locate the highest routing congestion.
Kind regards
GPK
Honored Contributor
